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FEATURES
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Greater than 2000 V ESD Protection Differential Linearity +1/2 LSB Tmin to Tmax Microprocessor Compatible Low Glitch Energy Gain Error Tempco (2 ppm/C max) Low Sensitivity to Amplifier Offset
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MP7645B
CMOS Buffered Multiplying 12-Bit Digital-to-Analog Converter
Four Quadrant Multiplication Latch-Up Free TTL/5 V CMOS Compatible Guaranteed Monotonic
GENERAL DESCRIPTION
The MP7645B is an improved precision, monolithic 12-bit CMOS 4-quadrant multiplying DAC with an on-board data latch. The latch is loaded by a single 12-bit wide word. Data is loaded into the input latch under the control of CS and WR inputs. These control inputs are level triggered; tying these inputs low makes the input latch transparent allowing direct unbuffered operation of the DAC. - Stability - The MP7645B incorporates a unique decoding technique yielding excellent accuracy and stability over tem-
SIMPLIFIED BLOCK DIAGRAM
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Rev. 2.00
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VREF CS WR
t a
VDD
S a
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perature. Monotonicity is guaranteed over the entire temperature range including the industrial and military ranges. The gain error specification of 2 ppm/C over a 100C temperature range equals 0.8 LSB of error.
- Digital Feedthrough - The MP7645B has 5 to 8 times less digital feedthrough than similar buffered DACs. - Low Sensitivity to Output Amplifier Offset - The additional linearity error incurred by amplifier offset is reduced by a factor of at least 3 in the MP7645B over conventional DACs. High latch-up resistance and high ESD protection make this a rugged, reliable attenuator!
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RFB
12-Bit Multiplying DAC 12 Input Data Latches
IOUT AGND
DGND
12 DB11-DB0
1
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MP7645B
ORDERING INFORMATION
Package Type
Plastic Dip Plastic Dip Ceramic Dip Ceramic Dip
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C
Part No.
MP7645BKN MP7645BLN MP7645BBD MP7645BCD
INL (LSB)
+1 +1/2 +1 +1/2
DNL (LSB)
+1 +1/2 +1 +1/2
Gain Error (% FSR)
+0.2 +0.2 +0.2 +0.2
PIN CONFIGURATION
See Packaging Section for Package Dimensions
IOUT AGND DGND (MSB) DB11 DB10 DB9 DB8 DB7 DB6 DB5
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
RFB VREF VDD WR CS DB0 (LSB) DB1 DB2 DB3 DB4
20 Pin CDIP, PDIP (0.300") D20, N20
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 NAME IOUT AGND DGND DB11 DB10 DB9 DB8 DB7 DB6 DB5 DESCRIPTION Current Output Port Analog Ground Digital Ground Data Input Bit 11 (MSB) Data Input Bit 10 Data Input Bit 9 Data Input Bit 8 Data Input Bit 7 Data Input Bit 6 Data Input Bit 5 PIN NO. 11 12 13 14 15 16 17 18 19 20 NAME DB4 DB3 DB2 DB1 DB0 CS WR VDD VREF RFB DESCRIPTION Data Input Bit 4 Data Input Bit 3 Data Input Bit 2 Data Input Bit 1 Data Input Bit 0 (LSB) Chip Select Input (Active Low) Write Input (Active Low) Positive Voltage Power Supply Reference Voltage Input Feedback Resistor Input
Rev. 2.00 2
MP7645B
ELECTRICAL CHARACTERISTICS
(VDD = + 15 V, VREF = +10 V unless otherwise noted)
25C Typ Tmin to Tmax Min Max
Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K, B L, C Differential Non-Linearity K, B L, C Gain Error K, B L, C Gain Temperature Coefficient2 Monotonicity K, L Power Supply Rejection Ratio Output Leakage Current K, L, B, C DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT Propagation Delay
Symbol
Min
Max
Units
Test Conditions/Comments FSR = Full Scale Range
N INL
12
12
Bits LSB End Point Linearity
+1 +1/2 DNL +1 +1/2 GE +0.2 +0.2 TCGE Guaranteed
+1 +1/2 LSB +1 +1/2 % FSR +0.2 +0.2 +2 Guaranteed 12-Bit Monotonic Tmin to Tmax ppm/C Gain/Temperature Using Internal RFB
PSRR IOUT
+50
+50
ppm/% nA
|Gain/VDD| VDD = + 5%
+10
+200
tS FT tPD
1 5 50
2 typ 5
s mV p-p ns
Full Scale Change to 1/2 LSB VREF = 10kHz, 20 Vp-p, sinewave From digital input change to 90% of final value
REFERENCE INPUT Input Resistance DIGITAL INPUTS3 Logical "1" Voltage Logical "0" Voltage Input Leakage Current Input Capacitance2 Data Control ANALOG OUTPUTS Output Capacitance2 COUT COUT 50 100 pF pF DAC Inputs all 0's DAC Inputs all 1's VIH VIL ILKG CIN CIN 3 +0.8 +1 5 20 3.0 +0.8 +10 5 20 V V A pF pF DB0-DB11 WR, CS RIN 7 11 25 7 25 k
Rev. 2.00 3
MP7645B
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter POWER SUPPLY Functional Voltage Range5 Supply Current SWITCHING CHARACTERISTICS2, 4 Chip Select to Write Set-Up Time Chip Select to Write Hold Time Write Pulse Width Data Valid to Write Set-Up Time Data Valid to Write Hold Time NOTES:
1 2 3 4 5
Symbol
Min
25C Typ
Max
Tmin to Tmax Min Max
Units
Test Conditions/Comments
VDD IDD
5
15 1
5
15 1
V mA
All digital inputs = 0 V or all = 5 V
tCS tCH tWR tDS tDH
180 0 100 100 10
ns ns ns ns ns
Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Digital Input Voltage to GND (2) . GND -0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . GND -0.5 to VDD +0.5 V VREF to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5 V (Functionality Guaranteed +0.5 V) Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . +300C Package Power Dissipation Rating to 75C CDIP, PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 13mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. 3 GND refers to AGND and DGND.
Rev. 2.00 4
MP7645B
WRITE CYCLE TIMING DIAGRAM
tCH
CS
tCS
VDD 0
WR
tWR tDH
VDD 0 VDD
tDS DATA IN (DB0-DB11) VIH VIL
DATA VALID 0
APPLICATION NOTES Refer to Section 8 for Applications Information
MICROPROCESSOR INTERFACING OF THE MP7645B
The MP7645B can interface directly to both 8- and 16-bit microprocessors via its 12-bit wide data latch using standard CS and WR control signals. A typical interface circuit for an 8-bit processor is shown (Figure 1.) This arrangement uses two memory addresses, one for the lower 8 bits of data to the DAC and one for the upper 4 bits of data into the DAC via the latch.
Figure 2. shows an alternative approach for use with 8-bit processors which have a full 16-bit wide address bus such as 6800, 8080 and Z80. This technique uses the 12 lower address lines of the processor addresses bus to supply data to the DAC, thus each MP7645B connected in this way uses 4k bytes of address locations. Data is written to the DAC using a single memory write instruction. The address field of the instruction is organized so that the lower 12 bits contain the data for the DAC and the upper 4 bits contain the address of the 4k block at which the DAC resides.
A15 A15 ADDRESS BUS A0 16-BIT ADDRESS BUS A0 4 ADDRESS DECODE DB11 12 DB0
Q0
ADDRESS DECODE CS
Q1
CS LATCH WR DB11 DB8
CPU
CPU
Q0
WR
CS WR
MP7645B
MP7645B
WR DB7 DB0
WR
DB7 DATA BUS DB0
DB7 8-BIT DATA BUS DB0
Q0 Q1
DECODED ADDRESS FOR DAC DECODED ADDRESS FOR LATCH
Figure 1. 8-Bit Processor to MP7645B Interface
Rev. 2.00 5
Figure 2. Connecting the MP7645B to 8-Bit Processors via the Address Bus
MP7645B
20 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D20
S1 See Note 1
20
S
11
1
10
E1 D Base Plane Seating Plane L b e b1 c L1 Q A E
INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN -- 0.014 0.038 0.008 -- 0.220 0.290 MAX 0.200 0.023 0.065 0.015 1.060 0.310 0.320
MILLIMETERS MIN -- 0.356 0.965 0.203 -- 5.59 7.37 MAX 5.08 0.584 1.65 0.381 26.92 7.87 8.13 NOTES -- -- 2 -- 4 4 7 5 -- -- 3 6 6 --
NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center.
0.100 BSC 0.125 0.150 0.015 -- 0.005 0 0.200 -- 0.070 0.080 -- 15
2.54 BSC 3.18 3.81 0.381 -- 0.13 0 5.08 -- 1.78 2.03 -- 15
Rev. 2.00 6
MP7645B
20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20
S
20 1 Q1 D
11 10 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN -- 0.015 0.014 0.038 0.008 0.945 0.295 0.220 MAX 0.200 -- 0.023 0.065 0.015 1.060 0.325 0.310
MILLIMETERS MIN -- 0.38 0.356 0.965 0.203 24.0 7.49 5.59 MAX 5.08 -- 0.584 1.65 0.381 26.92 8.26 7.87
0.100 BSC 0.115 0 0.055 0.040 (1) 0.150 15 0.070 0.080
2.54 BSC 2.92 0 1.40 1.02 3.81 15 1.78 2.03
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 7
MP7645B
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 8

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